`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Part of the project chess controller                        ////  
////                                                              ////
////                                                              //// 
////  Description                                                 //// 
////   -                                 //// 
////                                                              //// 
////  To Do:                                                      //// 
////   -                                //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales A, ale3191@gmail.com                //// 
////                                                              //// 
////////////////////////////////////////////////////////////////////// 
////                                                              //// 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 //// 
////                                                              //// 
//// This source file may be used and distributed without         //// 
//// restriction provided that this copyright statement is not    //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
////                                                              //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version.                                               //// 
////                                                              //// 
//// This source is distributed in the hope that it will be       //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //// 
//// PURPOSE.  See the GNU Lesser General Public License for more //// 
//// details.                                                     //// 
////                                                              //// 
//// You should have received a copy of the GNU Lesser General    //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////

module SevenSegmentDisplayController(
		input _clk_i,
		input [2:0] row_i,
		input  [2:0] column_i,
		input _rst_i,
		output reg [3:0]  seleccion7seg_o,
		output reg [7:0]  out_o
    );	
	 reg select;
	 reg [19:0] counter;

	 always @ (posedge _clk_i) begin
	 if (_rst_i == 1)begin
			select <= 0;
			seleccion7seg_o <= 0;
			out_o <= 0;
			counter <= 0;
			end 
	 else  if (counter == 20'h1FFFF)begin
		 if (select ==1) begin
			seleccion7seg_o <= 4'b0111;
			select <= !select;
			counter <= 0;
         case (column_i)
            4'b0000  : out_o <= 8'b11000000;
            4'b0001  : out_o <= 8'b11111001;
            4'b0010  : out_o <= 8'b10100100;
            4'b0011  : out_o <= 8'b10110000;
            4'b0100  : out_o <= 8'b10011001;
            4'b0101  : out_o <= 8'b10010010;
            4'b0110  : out_o <= 8'b10000010;
            4'b0111  : out_o <= 8'b11111000;
         endcase
		end 
		else begin	
				select <= !select;
				counter <= 0;
			seleccion7seg_o <= 4'b1101;
			case (row_i)
            4'b0000  : out_o <= 8'b11000000;
            4'b0001  : out_o <= 8'b11111001;
            4'b0010  : out_o <= 8'b10100100;
            4'b0011  : out_o <= 8'b10110000;
            4'b0100  : out_o <= 8'b10011001;
            4'b0101  : out_o <= 8'b10010010;
            4'b0110  : out_o <= 8'b10000010;
            4'b0111  : out_o <= 8'b11111000;

         endcase
		end 
		end 
	 else 		counter <= counter + 1;

		end
endmodule